This invention relates to a method for constructing delay circuits in an integrated circuit (IC) formed by a master slice approach (hereinafter referred to as a master slice IC).
ICs generally require delay circuits to eliminate differences in operating speeds among elements, etc. Master slice ICs, however, do not have the elements for delay circuits. Unlike full custom ICs, they are composed of a plurality of transistors, or basic cells, of identical patterns formed beforehand on a semiconductor substrate (see, for example, U.S. Pat. No. 3,943,551, Skorup, LSI Array Using Field Effect Transistor of Different Conductive Type) and only require selective connection of the transistors by an aluminum wiring to obtain the desired logic gates, such as inverters. Therefore, it is difficult at the wiring stage to add resistance and capacitance (RC) elements on the semiconductor substrate to construct the delay circuits.
To obtain the necessary delay time in master slice ICs, therefore, the signal transmission times through the logic gates are conventionally utilized. However, the signal transmission times through a logic gate, i.e., the delay time from the input time to the output time of a logic gate, is very small. Therefore, a great number of logic gates must be connected in series in order to obtain the desired delay time. Further, the delay time derived from a logic gate varies depending on the position in which the logic gate is arranged, the capacitance of the wiring lines, the temperature, and the manufacturing process. For example, the transmission delay time of a one-stage inverter may vary from half to twice a standard value, depending on the conditions. Therefore, it is difficult to precisely obtain a desired delay time by utilizing conventional logic gates in master slice ICs.